As a main manner of high-density integration of packages currently, PoP attracts more and more attention. However, the increase of stacked packages leads to a problem of heat dissipation, which becomes one of the bottlenecks that hinder PoP applications.
Chip stacking is one of the main means of improving high-density integration of electronic packages, and a PoP design has been developed and applied in the industry widely. A typical two-layer PoP design is shown in FIG. 1. A layer-2 package 13 is welded onto a layer-1 package 11 through a reflow process of solder balls. For a PoP design with more layers, the foregoing process may be repeated. To prevent interference between the layer-1 chip and the layer-2 carrier board, the diameter of a solder ball 12 around the layer-2 carrier board is generally designed as greater than the height of the chip. In this way, a certain gap exists between the layer-1 chip and the layer-2 carrier board. Through the gap, a cooling fan can dissipate heat for the chip.
The PoP design can improve package density, but is not helpful for heat dissipation of the chip. On the contrary, multiple chips are stacked together, heat accumulates inside the PoP packages, and the heat dissipation performed by the cooling fan through the gap between the chip and the carrier board can hardly meet requirements. The heat dissipation of the PoP becomes a main bottleneck of high-density PoP integration.
Therefore, persons skilled in the art are urgently seeking a technical solution to improving heat dissipation capabilities of PoP packages while ensuring high density and miniaturization of PoP packages.